There are increasing concerns about possible malicious modifications ofintegrated circuits (ICs) used in critical applications. Such attacks are oftenreferred to as hardware Trojans. While many techniques focus on hardware Trojandetection during IC testing, it is still possible for attacks to go undetected.Using a combination of new design techniques and new memory technologies, wepresent a new approach that detects a wide variety of hardware Trojans duringIC testing and also during system operation in the field. Our approach can alsoprevent a wide variety of attacks during synthesis, place-and-route, andfabrication of ICs. It can be applied to any digital system, and can be tunedfor both traditional and split-manufacturing methods. We demonstrate itsapplicability for both ASICs and FPGAs. Using fabricated test chips with Trojanemulation capabilities and also using simulations, we demonstrate: 1. The areaand power costs of our approach can range between 7.4-165% and 0.07-60%,respectively, depending on the design and the attacks targeted; 2. The speedimpact can be minimal (close to 0%); 3. Our approach can detect 99.998% ofTrojans (emulated using test chips) that do not require detailed knowledge ofthe design being attacked; 4. Our approach can prevent 99.98% of specificattacks (simulated) that utilize detailed knowledge of the design beingattacked (e.g., through reverse-engineering). 5. Our approach never producesany false positives, i.e., it does not report attacks when the IC operatescorrectly.
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